Espressif Systems /ESP32-P4 /SYSTIMER /CONF

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Interpret as CONF

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SYSTIMER_CLK_FO)SYSTIMER_CLK_FO 0 (ETM_EN)ETM_EN 0 (TARGET2_WORK_EN)TARGET2_WORK_EN 0 (TARGET1_WORK_EN)TARGET1_WORK_EN 0 (TARGET0_WORK_EN)TARGET0_WORK_EN 0 (TIMER_UNIT1_CORE1_STALL_EN)TIMER_UNIT1_CORE1_STALL_EN 0 (TIMER_UNIT1_CORE0_STALL_EN)TIMER_UNIT1_CORE0_STALL_EN 0 (TIMER_UNIT0_CORE1_STALL_EN)TIMER_UNIT0_CORE1_STALL_EN 0 (TIMER_UNIT0_CORE0_STALL_EN)TIMER_UNIT0_CORE0_STALL_EN 0 (TIMER_UNIT1_WORK_EN)TIMER_UNIT1_WORK_EN 0 (TIMER_UNIT0_WORK_EN)TIMER_UNIT0_WORK_EN 0 (CLK_EN)CLK_EN

Description

Configure system timer clock

Fields

SYSTIMER_CLK_FO

systimer clock force on

ETM_EN

enable systimer’s etm task and event

TARGET2_WORK_EN

target2 work enable

TARGET1_WORK_EN

target1 work enable

TARGET0_WORK_EN

target0 work enable

TIMER_UNIT1_CORE1_STALL_EN

If timer unit1 is stalled when core1 stalled

TIMER_UNIT1_CORE0_STALL_EN

If timer unit1 is stalled when core0 stalled

TIMER_UNIT0_CORE1_STALL_EN

If timer unit0 is stalled when core1 stalled

TIMER_UNIT0_CORE0_STALL_EN

If timer unit0 is stalled when core0 stalled

TIMER_UNIT1_WORK_EN

timer unit1 work enable

TIMER_UNIT0_WORK_EN

timer unit0 work enable

CLK_EN

register file clk gating

Links

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